Processors and SoCs (System-on-Chip) are power constrained and employ power gating to “turn off” blocks (i.e., to enter sleep state for logic blocks) which are not in use, saving leakage power. Traditionally, switching a block into sleep state requires time in order to save any data which must be retained for correct operation. This data may be stored in embedded memory arrays, flip-flops, and latches and takes time to save into “Always-ON” storage, as well as time to restore the stored data when power is again applied to the logic block. Saving and restoring data limits how frequently the logic block can be power gated, and also incurs a power penalty which reduces the overall gains.
The standard method for saving and restoring data involves moving the data into a memory array which is always powered up. Alternatively, state retention flip-flops can used to locally save the required data in the flip-flops themselves, by isolating a portion of the flip-flop and connecting it to an Always-ON supply. These flip-flops allow fast save and restore since the state (i.e., data) does not need to be moved into a memory array which is always powered up. However, such flip-flops require an Always-ON supply to be routed to every state retention flip-flop, and a portion of the flip-flop consumes leakage power even during sleep mode.